Many integrated circuits include memory cells that are repeatedly written to, read, and erased. Each time a memory cell is written to, it is referred to as a “cycle” of that memory cell. Memory cells with floating gates are written to by injecting electrons into the floating gate from a drain. As the memory cell is repeatedly cycled, some electrons may become trapped, or build up, in the area between the drain and the floating gate. This build up of a charge produces a “pseudo” negative gate bias that produces field effects at a substrate surface underlying the floating gate. With repeated cycling, this charge build up produces gate induced drain leakage, and can result in the memory cell failing to save a charge, so the write process fails.
A drain silicide typically overlies the drain and facilitates electrical contact with other components of the integrated circuit. The memory cell is positioned overlying a channel defined between a source and the drain, where the source and drain are utilized in operation of the memory cell. It has been discovered that increasing the distance between the drain silicide and the floating gate reduces the gate induced drain leakage that develops with repeated cycling. Integrated circuits are becoming smaller and smaller as time goes by, and the area of the source may be reduced to the point that increasing the distance between the source silicide and the floating gate results in the source silicide being eliminated or reduced such that good electrical contact is compromised. However, the area of the drain may be larger than that of the source, so there may be more space available on the drain side for increasing the distance between the drain silicide and the floating gate. Production processes tend to be the same for the source silicide and the drain silicide to reduce manufacturing costs, so processes that produce different structures on the drain and the source side are not typical.
Accordingly, it is desirable to provide integrated circuits with memory cells that are resistant to gate induced drain leakage resulting from repeated cycling, and methods for producing the same. In addition, it is desirable to provide integrated circuits with increased distance between the drain silicide and the floating gate, without increasing the distance between the source silicide and the floating gate, and methods of producing the same. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.